Switch-timing in a switched-capacitor power converter

ABSTRACT

In a power converter, each gate-driving circuit uses charge from a selected pump capacitor operate a corresponding switch. The switches transitions between different states, each of which corresponds to a particular interconnection of pump capacitors. During clocked operations, the first switch closes, thereby establishing a connection with the first pump capacitor. Prior to the first switch closing, the second switch closes.

RELATED APPLICATIONS

This application is a reissue application of U.S. application Ser. No.16/146,086, filed Sep. 28, 2018, now U.S. Pat. No. 10,374,512, which isa continuation-in-part of U.S. application Ser. No. 13/837,796, filed onMar. 15, 2013, the contents of which are herein incorporated byreference in their entirety.

FIELD OF INVENTION

This invention relates to switched-capacitor power-converters, and moreparticularly to efficient gate drivers for such converters.

BACKGROUND

A switch-mode power converter is a specific type of power converter thatproduces an output voltage by switching energy-storage elements (i.e.inductors and capacitors) into different electrical configurations usinga switch network. A switched-capacitor power-converter is a type ofswitch-mode power converter that primarily utilizes capacitors totransfer energy. In such converters, the number of capacitors andswitches increases as the conversion gain increases.

As used herein, conversion gain represents a voltage gain if theswitched-capacitor power-converter produces an output voltage that islarger than the input voltage or a current gain if theswitched-capacitor power-converter produces an output voltage that issmaller than the input voltage.

SUMMARY

In one aspect, the invention features a switched-capacitorpower-converter having gate-driving circuits, each of which uses chargefrom a selected pump capacitor from a plurality of pump capacitors tooperate a corresponding switch from a first plurality of switches, amongwhich is a first switch. During clocked operation of theswitched-capacitor power-converter, the first plurality of switchestransitions between different states, each of which corresponds to aparticular interconnection of the pump capacitors. During clockedoperation, the first switch closes, thereby establishing a connectionwith a first pump capacitor from the plurality of capacitors. Prior tothe first switch closing, a second switch closes. As a result of thesecond switch having closed, the first pump capacitor is pre-charged bythe time the first switch closes.

In some embodiments, the second switch is connected such that, when thesecond switch closes, a voltage arises across the first pump capacitor.

Embodiments also include those in which the second switch connects tothe first pump capacitor's anode and those in which the second switchconnects to the first pump capacitor's cathode.

In some embodiments, closing the second switch connects the first pumpcapacitor to a phase voltage. Among these are embodiments in which thesecond switch and the first switch are synchronized in operation andthose in which they are asynchronous. Among these are embodiments inwhich the first and second switches close concurrently and those inwhich the second switch closes before the first switch closes. In someof these embodiments, there exists a fixed time interval between closingthe second switch and closing the first switch.

Also among the embodiments are those that include a pre-charging circuitconfigured to limit voltage across the switches from the first pluralityof switches during power-up of the switched-capacitor power-converter.

Some embodiments further include a phase generator that includes phaseswitches, one of which is the second switch. Among these are embodimentsin which the phase generator provides first and second phase voltages.In these embodiments, the second switch provides the first phase voltageupon closure thereof and a third switch, which is also part of the phasegenerator, when closed, provides the second phase voltage. The firstplurality of switches includes first and second subsets of switches.Switches in the first subset open and close together. Switches in thesecond subset open and close together, but at times that differ fromtimes at which the switches in the first subset open and close together.The first switch is in the first subset; the second switch issynchronized with switches in the first subset; and the third switch issynchronized with switches in the third subset. In some of theseembodiments, as a result of being synchronized with switches in thefirst subset, the second switch closes prior to closure of all switchesin the first subset, and, as a result of being synchronized withswitches in the second subset, the third switch closes prior to closureof all switches ins the first subset.

Some embodiments further include a control block that comprisescircuitry that is configured to provide a first plurality of drivesignals and to provide a second plurality of drive signals. Each drivesignal from the first plurality of drive signals is connected to agate-driving circuit that drives a gate of a transistor from a firstplurality of transistors. Each drive signal from the second plurality ofdrive signals is connected to a gate-driving circuit that drives a gateof a transistor from a second plurality of transistors. The drivesignals from the first plurality of drive signals cooperate to cause alltransistors that are in the first plurality of transistors to closetogether following closure of the second switch. The drive signals fromthe second plurality of drive signals cause all transistors in thesecond plurality of transistors to close together following closure of athird switch from the second plurality of switches. Among theseembodiments are those in which the circuitry comprises a level shifterthat is configured to receive first and second voltages and to transformthe first and second voltages into third and fourth voltages. In theseembodiments, the level shifter is configured to present a voltagedifference that is equal to a difference between the third and fourthvoltage to a gate terminal of a transistor that is from the firstplurality of transistors.

Some embodiments further include a phase generator comprising the secondplurality of switches. The phase generator provides a time-varyingvoltage level to one terminal of each of the pump capacitors and togenerate a voltage level for at least one pump capacitor in a firstcharge-transfer path using a voltage from a pump capacitor in a secondcharge-transfer path.

In another aspect, the invention features a switched-capacitorpower-converter having first and second pluralities of switches andgate-driving circuits corresponding to the switches in the firstplurality of switches. The gate-driving circuits rely on charge on pumpcapacitors to cause the switches from the first plurality of switches totransition between states. The switched-capacitor power-converterundergoes clocked operation having consecutive clock cycles. During eachclock cycle, a switch from the second plurality of switches connects tofirst and second pump capacitors and then a first switch from the firstplurality of switches connects to the first pump capacitor and a secondswitch from the first plurality of switches connects to the second pumpcapacitor.

In some embodiments, the switch from the second plurality of switchesconnects to the first and second pump capacitors the first and secondpump capacitors begin to charge.

In other embodiments, when the first and second switches from the firstplurality of switches connect to the first and second pump capacitors,the first and second pump capacitors begin to discharge.

In yet other embodiments, while the switch from the second plurality ofswitches is connected to the first and second pump capacitors, a thirdpump capacitor is being discharged.

In another aspect, the invention features a switched-capacitorpower-converter that comprises first and second pluralities of switchesand gate-driving circuits corresponding to the switches in the firstplurality of switches. The gate-driving rely on charge stored on pumpcapacitors to cause the switches from the first plurality of switches totransition between states. The switched-capacitor power-converterundergoes clocked operation that consists of consecutive clock cycles,each of which includes a portion during which at most a second switchfrom the second plurality of switches is connected to the pumpcapacitors.

In another aspect, the invention features a switched-capacitorpower-converter that comprises first and second pluralities of switchesand gate-driving circuits corresponding to the switches in the firstplurality of switches. The gate-driving circuits rely on charge on pumpcapacitors to cause the switches from the first plurality of switches totransition between states. The switched-capacitor power-converterundergoes clocked operation that defines consecutive clock cycles.During each clock cycle, a switch from the second plurality of switchesconnects to a first pump capacitor and then a first switch from thefirst plurality of switches connects to the first pump capacitor.

In some embodiments, when the switch from the second plurality ofswitches connects to the first pump capacitor, the first pump capacitorbegins to charge.

In other embodiments, the switch from the second plurality of switchesconnects to both the first pump capacitor and a second pump capacitor,and wherein, after the switch from the second plurality of switches hasclosed, a second switch from the first plurality of switches connects toa second pump capacitor.

In yet other embodiments, while the switch from the second plurality ofswitches is connected to the first pump capacitor, a second pumpcapacitor is being discharged.

Other features and advantages of the invention are apparent from thefollowing description, and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a single-phase cascade-multiplier with cascoded switchesand corresponding gate drivers and a pre-charging circuit;

FIG. 2 shows the cascade multiplier of FIG. 1 in a firstoperating-phase;

FIG. 3 shows the cascade multiplier of FIG. 1 in a secondoperating-phase;

FIG. 4 shows a tapered gate-driver used to drive stack switches in thecascade multiplier of FIG. 1 ;

FIG. 5 shows a cascoded gate-driver used to drive stack switches in thecascade multiplier of FIG. 1 ;

FIG. 6 shows a dual-phase cascade-multiplier with cascoded switches andcorresponding gate drivers;

FIG. 7 shows the cascade-multiplier of FIG. 6 in one of two states ofoperation;

FIGS. 8 and 9 show a dual-phase cascade multiplier and correspondinggate drivers;

FIGS. 10-12 shows different phase generators for use with the circuitsshown in FIGS. 8 and 9 ;

FIG. 13 shows a dual-phase series-parallel switched-capacitor converterand corresponding gate drivers; and

FIG. 14 shows a power converter that includes a cascade multiplier asshown in the preceding figures.

DETAILED DESCRIPTION

Referring to FIG. 1 , a first cascade-multiplier 30 that has acharge-transfer path extending between a high-voltage terminal VO and alow-voltage terminal VI. The charge-transfer path includes transistorsM0-M5 that interconnect pump capacitors C1-C3. More specifically, thecharge-transfer path has three stack-nodes. Because there is only onecharge-transfer path, the first cascade multiplier 30 is considered tobe a “single-phase” cascade multiplier.

Each stack node connects to a pair of transistors and also to a pumpcapacitor. At a first stack-node, first and second transistors M0, M1connect to an anode of a first pump-capacitor C1. The cathode of thefirst pump-capacitor C1 connects to a first phase-node on which ispresent a first phase-voltage VP1. The first phase-voltage VP1 typicallyarises by opening and closing first phase-switches at the desiredfrequency.

At a second stack-node, third and fourth transistors M2, M3 connect tothe anode of a second pump-capacitor C2, the cathode of which connectsto a second phase-node on which is present a second phase-voltage VP2that is out-of-phase with the first phase-voltage VP1. The secondphase-voltage VP2 typically arises by opening and closing secondphase-switches at the desired frequency.

At a third stack-node, fifth and sixth transistors M4, M5 connect to theanode of a third pump-capacitor C3, the cathode of which connects to thefirst phase-node.

For ease of exposition, the transistors M0-M5 will sometimes be referredto as “switches” or “stack switches.” The states of these switches willbe referred to as “open” and “closed.” In the “closed” state, which issometimes called the “on” state, the switch allows current to flowthrough it. In the “open” state, which is sometimes called the “off”state, the switch suppresses flow of current through it.

The embodiment illustrated in FIG. 1 features cascoded second and thirdtransistors M1, M2 to couple the first and second pump capacitors C1, C2Similarly, the fourth and fifth transistors M3, M4 are cascoded tocouple the second and third pump capacitors C2, C3. However, it ispossible to use single transistors instead of cascoded transistors whilestill reaping some of the advantages described herein.

Each of the transistors M0-M5 implements a switch. To open and closethese switches requires causing charge to flow in and out of a metalplate that lies over a gate region of these transistors M0-M5. The actof causing such charge flow in and out of this metal plate is referredto herein as “driving” the transistor. The metal plate will be referredto herein as the “gate terminal” of the transistor.

The charge that flows in and out of a transistor's gate terminal duringthe driving process comes from a donor capacitor. In the embodimentshown, which has only one charge-transfer path, the donor capacitor isone of the pump capacitors on the same charge-transfer path as thetransistor.

In the case of a multi-phase converter, which has multiplecharge-transfer paths, the donor capacitor is a pump capacitor that ison another charge-transfer path.

A driver set 32 includes first, second, third, and fourth voltagefollowers 36A-36D that receive corresponding first, second, third, andfourth bias voltages V1-V4. It also includes circuitry that causes theswitches M0-M5 to open and close in response to drive signals A0, B0,B1, A1, A2, B2 provided by level shifters within a control block 33. Thecontrol block 33 generates its drive signals A0, B0, B1, A1, A2, B2 inresponse to a clock signal CLK.

The driver set 32 implements two kinds of drivers: a low-voltage driver34 and a high-voltage driver 35, both of which rely on a circuit acrosswhich a supply voltage is maintained during operation. The maindifference is that the high-voltage driver 35 incorporates a circuitthat supports twice the supply voltage as that used in a low-voltagegate driver 34. Because of their locations within the circuit, ahigh-voltage driver 35 is the best choice for driving the second andfourth transistors M1, M3. The remaining four transistors M0, M2, M4, M5require only a low-voltage driver 34.

Each driver 34, 35 connects to the gate terminal of a corresponding oneof the transistors M0-M5. In particular, the two high-voltage drivers 35connect to corresponding gates of the second and fourth transistors M1,M3. The four low-voltage drivers 34 connect to the remaining first,third, fifth, and sixth transistors M0, M2, M4, M5.

A typical drive-signal A0, B0, B1, A1, A2, B2 from the control block 33is a square wave. Each level shifter within the control block 33 ensuresthat the square wave spans a voltage range that conforms to theperformance requirements of the circuit that implements itscorresponding gate driver 34, 35.

The square wave's upward transitions trigger release of a flow of chargefrom the gate driver 34, 35 and into the corresponding transistor'sgate. This rapidly floods the transistor's gate terminal with charge,which then rapidly forms an electric field in the transistor's gateregion. This electric field forms a conducting channel so that thetransistor is able to conduct current between its drain and sourceregions. This amounts to closing the switch.

The square wave's downward transitions trigger the rapid evacuation ofcharge from the transistor's gate terminal, thus dissipating theelectric field and collapsing the conducting channel in the gate region.As a result, the drain and source regions are once more isolated fromeach other. This amounts to opening the switch.

As the first cascade-multiplier 30 operates, the switches M0-M5transition between three different states.

In a first state, the control block 33 opens all switches from a firstsubset of stack switches M0, M3, M4 and closes all switches from asecond subset of stack switches M1, M2, M5. This is shown in FIG. 2 , inwhich dashed lines represent transistors in a non-conducting state.

In a second state, the control block 33 closes the switches from thefirst subset M0, M3, M4 and opens the switches from the second subsetM1, M2, M5. This is shown in FIG. 3 , in which dashed lines representtransistors in a non-conducting state.

And in a third state, which occurs between the first and second state,the control block 33 opens all of the switches M0, M1, M2, M3, M4, M5.The placement of this third state between the first and second states intime reduces the possibility of having switches from the first andsecond subsets open at the same time.

For convenience in exposition, drive signals for switches in the firstsubset are labeled by alphanumeric strings that begins with “A” anddrive signals from a second set are labeled by alphanumeric strings thatbegin with a “B.” The drive signals A0, B0, B1, A1, A2, B2 controlcorresponding transistors M0, M1, M2, M3, M4, M5.

As described in more detail below, at least some of the gate drivers 34,35 are powered from the pump capacitors C1-C3 in the charge-transferpath. The voltage across each of the pump capacitors C1-C3 is a fractionof the high voltage drop between the voltage at the high-voltageterminal VO and the voltage at the low-voltage terminal VI. Thispromotes efficient generation of gate-driving signals that maintaindesired limits on the gate-to-source voltages of the transistors M0-M5.

Each of the voltage followers 36A-36D receives a first voltage from acorresponding one of the pump capacitors C1-C3 and provides a constantsecond voltage to the corresponding gate-drivers 34, 35. The secondvoltage is equal to or lower than the first voltage.

When a particular voltage-follower, for example the firstvoltage-follower 36A, provides a second voltage that is equal to thefirst voltage, the first voltage-follower 36A behaves like a switch. Toachieve this behavior, the first, second, and third bias voltages V1-V3are at least a threshold voltage above the corresponding source voltagewhile the fourth bias voltage V4 is at least a threshold voltage belowthe corresponding source voltage. The voltage followers 36A-36Dexperience the same voltage stress as the transistors M0-M5 in the firstcascade-multiplier 30.

Also illustrated in FIG. 1 is an example of a pre-charge circuit 38 thatcarries out certain functions just before clocked operation of the firstcascade-multiplier 30 begins.

The pre-charge circuit 38 initializes the voltages on the pumpcapacitors C1-C3 before clocked operation of the firstcascade-multiplier 30 actually begins. It also charges any parasiticcapacitances inherent in the circuit. Pre-charging the pump capacitorsC1-C3 helps maintain the drain-to-source voltages across the transistorsM0-M5 within required limits during startup. In addition, thepre-charged pump capacitors C1-C3 power the gate drivers immediatelyupon the start of clocked operation of the first cascade-multiplier 30.Once clocked operation has begun, the pre-charge circuit 38 can bedisabled.

To facilitate the use of low-voltage transistors, the pre-charge circuit38 uses a combination of low-voltage transistors and bias resistors. Aresistor divider sets up the pre-charge voltage for each of the pumpcapacitors C1-C3 during startup. The source voltage of each transistorwithin the pre-charge circuit 38 is at least a threshold voltage belowits corresponding gate voltage. This avoids the risk of exposing any ofthe transistors, either in pre-charge circuit 38 or in the firstcascade-multiplier 30, to device-damaging voltage stresses, eitherduring startup or during clocked operation.

The first cascade-multiplier 30 transfers energy from a source 16 to aload 18 by cycling between the first and second states at a specificfrequency. All of the transistors coupled with the “A” drive signals areactivated and de-activated at the same time; as is the case for all ofthe transistors coupled with the “B” drive signals. To ensure a cleantransition between the first and second state, the “A” signals and “B”signals are non-overlapping. In particular, the “A” and “B” signals areseparated in time by the duration of the third state.

Operation of the first cascade-multiplier 30 also requires the presenceof first and second phase voltages VP1, VP2 at the first and secondphase nodes. A phase generator 110, best seen in FIGS. 8 and 9 and inmore detail in FIGS. 10-12 generates these phase voltages throughsequential opening and closing of phase switches ML1, ML2, MH1, MH2. Inthe illustrated embodiment, the phase generator 110 does so by using avoltage at the anodes of pump capacitors C1A, C1B, which connect tocorresponding supply inputs NC1, NC2 of the phase generator 110.However, any convenient capacitor can be used to supply the necessaryvoltage. For example, in the configuration shown in FIG. 8B,voltage-following capacitors Ca, Cb can be used.

The particular phase generator 110 provides four phase voltages VP1,VP2, VP3, VP4, as shown in FIG. 8 . However, it is a simple matter toadapt it to generate only the two phase-voltages VP1, VP2 that arerequired for a single-phase cascade-multiplier 30 as shown in FIG. 1 .

The first and second phase voltages VP1, VP2 are synchronized with the“A” signals and “B” signals, and thus, with opening and closing of thestack switches M0-M5.

Some embodiments achieve synchronization by opening and closing phaseswitches ML1, MH1, ML2, MH2 at the same time that corresponding stackswitches transition out of the third state M0-M5. Other embodimentsachieve synchronization by opening and closing the phase switches ML1,MH1, ML2, MH2 at times that are at some fixed interval before or afterthe corresponding stack switches M0-M5 transition out of the thirdstate. In a particularly preferred practice, the phase switches close atsome fixed interval before the stack switches M0-M5 transition out ofthe third state. This creates a brief interval during which the phaseswitches ML1, MH1, ML2, MH2 are already closed while the stack switchesM0-M5 are still open. After the lapse of this brief interval, the stackswitches M0-M5 transition out of the third state. As a result, the phaseswitch and the corresponding stack switches will both be closed.

Assuming an input voltage of five volts at the low-voltage terminal VI,the first cascade-multiplier 30 produces a twenty-volt output voltage atthe high-voltage terminal VO. The maximum voltage across any transistoris five volts. Furthermore, the low-voltage gate drivers 34 support fivevolts while the high-voltage gate drivers 35 must support ten volts.

Upon commencement of the first state, shown in FIG. 2 , the first phasevoltage VP1 will have been at five volts while the second phase voltageVP2 will have been at zero volts. The gate drivers that receive a “B”signal activate their corresponding transistors and the gate driversthat receive an “A” signal de-activate their corresponding transistors.Consequently, a gate voltage of fifteen volts activates the second,third, and sixth transistors M1, M2, M5 while gate voltages of fivevolts, ten volts, and fifteen volts de-activate the first, fourth, andfifth transistors M0, M3, M4, respectively.

In contrast, FIG. 3 illustrates the second state, which begins shortlyafter the first and second phase voltage VP1, VP2 have reached zero andfive volts respectively. When transitioning from the third state to thesecond state, the gate drivers that receive an “A” signal activate theircorresponding transistors and the gate drivers that receive a “B” signalde-activate their corresponding transistors. Consequently, gate voltagesof five volts, ten volts, and twenty volts de-activate the transistorsM1, M2, M5, respectively; while gate voltages of ten volts, twentyvolts, and twenty volts activate the transistors M0, M3, M4,respectively.

In the course of opening and closing a transistor M0, M1, M2, M5, chargeflows towards and away from the gate terminals of those transistors.This charge inevitably passes between the source and drain of thevoltage follower 36A-36D associated with that transistor. Since thereexists a five-volt drop between a voltage follower's drain and sourceterminals, this current from its source to its drain represents lostpower. In the case of the second, third, and sixth transistors M1, M2,M5, this power loss occurs during the first state. In the case of thefirst transistor M0, this occurs during the second state. The fourthtransistor M3 and the fifth transistor M4 do not have associated voltagefollowers. Hence, this difficulty does not arise for those transistors.

In the first cascade-multiplier 30, charge transfers to a load 18 from asource 16 at a rate dictated by the load 18. Because the firstcascade-multiplier 30 is a single-phase cascade-multiplier, there isonly one charge-transfer path along which charge can be transferred.

For example, at the start of a first clock-cycle, a charge leaves thesource 16 and flows into the first pump-capacitor C1. After a statetransition, the charge moves to the second pump-capacitor C2. When asecond clock-cycle begins, the charge moves from the secondpump-capacitor C2 to the third pump-capacitor C3. After one more statetransition, the charge finally reaches the load 18. Thus, the timerequired for the charge to traverse the charge-transfer path from thesource 16 to the load 18 was the time for two full clock cycles, or fourconsecutive states.

In general, as the conversion gain of a cascade multiplier increases,the number of pump capacitors increases. Consequently, it takes a longertime for a charge from the source 16 to reach the load 18 because thecharge needs to traverse more pump capacitors. For theswitched-capacitor topologies shown, the number of clock cycles in thecharge-transfer path is two less than the conversion gain. In theillustrated example, the conversion gain is equal to four. Therefore,the number of clock cycles is two.

FIGS. 4-5 illustrate two alternative designs of the gate drivingcircuits, both of which can be used for the high-voltage drivers 35 andthe low-voltage drivers 34. However, as will be made clear in thefollowing description, the gate driver in FIG. 4 is more suitable forthe low-voltage gate driver 34 while the gate driver in FIG. 5 is moresuitable for the high-voltage gate driver 35.

The first alternative design, shown in FIG. 4 , has an input terminalIN, an output terminal OUT, and first and second supply terminals VDD,VSS. The input terminal IN couples with the output terminal OUT throughfirst, second, third, and fourth inverters, in that order. Each inverterhas a high-side PMOS transistor MP1-MP4 and a corresponding low-sideNMOS transistor MN1-MN4. Due to the difference between electron and holemobilities, each of the PMOS transistors MP1-MP4 is typically sizedlarger than its corresponding NMOS transistor MN1-MN4.

Starting at the input terminal IN, each subsequent inverter is k timeslarger than the previous inverter. For example, if k is equal to fiveand the width of the first inverter is one micron, then the widths ofthe second, third, and fourth inverters are five microns, twenty-fivemicrons, and one hundred and twenty-five microns, respectively. For thisreason, the design shown in FIG. 4 is often called a “taperedgate-driver.” By tapering the inverters, a small logic gate coupled tothe input terminal IN is able to drive a large power transistor coupledto the output terminal OUT.

The maximum supply voltage of the tapered gate-driver is less than orequal to the breakdown voltage of the transistors. Therefore, thetapered gate-driver is a good choice for the low-voltage gate drivers 34in the first cascade-multiplier 30. Unfortunately, due to the highervoltage requirements of the high-voltage gate-driver 35 in FIGS. 1-3 ,the tapered gate-driver requires transistors with twice the breakdownvoltage.

A cascoded gate-driver, as shown in FIG. 5 , avoids this difficulty.Unlike the tapered gate-driver, the cascoded gate-driver permitsincreasing the supply voltage while avoiding the need of higher voltagetransistors.

The cascoded gate driver includes an input terminal IN, an outputterminal OUT, and supply terminals VDD, VSS. The cascoded gate driverfeatures an output stage that includes first and second high-sidetransistors MP5, MP6 and first and second low-side transistors MN5, MN6.The output stage requires additional support circuitry, such as a levelshifter, two gate-drivers, a delay block, and a voltage regulator, allof which can be designed using transistors with the same breakdownvoltage as that of the transistors in the output stage.

During normal operation of the cascoded gate driver, the high-sidetransistors MP5, MP6 are activated when the low-side transistors MN5,MN6 are de-activated and vice-versa. Therefore, two de-activatedtransistors are always available to support the differential voltageacross the supply terminals VDD, VSS. This means that the cascodedgate-driver can support twice the supply voltage.

In general, a larger number of transistors can be cascoded to increasethe supply voltage further. For example, if the output stage includedthree high-side transistors and three low-side transistors then themaximum supply voltage would be tripled and so on. Unfortunately, as thenumber of cascoded transistors increases, so does the complexity of thesupport circuitry.

Unlike a single-phase cascade-multiplier, such as the firstcascade-multiplier 30, a multi-phase cascade-multiplier has two or morecharge-transfer paths that operate temporally out-of-phase with eachother.

FIG. 6 shows second cascade-multiplier 40 constructed by placing twocopies of the single-phase cascade-multiplier 30 in parallel. Each copyof the single-phase cascade-multiplier will be referred to as a “phase.”

The second cascade-multiplier 40 features a first phase and a secondphase. The first phase includes a first set of pump capacitors C1A-C3A,a first set of transistors M0A-M5A, and a first first-phase-voltage VP1and a second first-phase-voltage VP2. The second phase includes a secondset of pump capacitors C1B-C3B, a second set of transistors MOB-M5B, afirst second-phase-voltage VP3 and a second second-phase-voltage VP4.

Each of the transistors M0A-M5B has a corresponding gate driver 34 thatreceives a driver signal with a label either beginning with an “A” or a“B.” The first phase includes first-phase drive-signals A0a-B2a whilethe second phase includes second-phase drive-signals A0b-B2b.

The phase difference between the first-phase drive-signals A0a-B2a andthe second-phase drive-signals A0b-B2b achieved by swapping the “A” and“B” signals in one of the two phases and then inverting thecorresponding phase voltages. For example, in normal operation, thefirst first-phase voltage VP1 and the first second-phase voltage VP3 arein a state that is complementary to that of the second first-phasevoltage VP2 and the second second-phase voltage VP4.

The voltage followers in the first phase receive first-phasebias-voltages V1a-V4a. The voltage followers in the second phase receivesecond-phase bias-voltages V1b-V4b.

A control circuit generates the first-phase bias voltages V1a-V4a, thesecond-phase bias-voltages V1b-V4b, the first-phase drive-signalsA0a-B2a and the second-phase drive-signals A0b-B2b.

When the source 16 and the load 18 trade places, a step-downpower-converter becomes a step-up converter and vice versa. Therefore,the second cascade-multiplier 40 is a step-down power-converter insteadof a step-up power-converter, as was the case for the firstcascade-multiplier 30.

The second cascade-multiplier 40 operates as described in connectionwith FIGS. 1-3 . Assuming a twenty-volt input voltage at the low-voltageterminal VI, the resulting voltage levels powering the gate drivingcircuits can be understood with reference to FIG. 7 , which shows thefirst operating-state. Depicting the second operating-state is notnecessary since it is simply a mirror image of the first operating-statealready shown in FIG. 7 .

There are several benefits of dual-phase construction over single-phaseconstruction.

One benefit is that a charge-transfer path will always exist between thesource 16 and the load 18 regardless of the state of operation.

Another benefit is that the one phase can derive energy from analternate phase to power circuitry and vice versa. This allows thesecond cascade-multiplier 40 to only use low-voltage gate drivers 34.

Yet another benefit is that there are fewer voltage followers required.This is because the transistors M0A-M3B derive power from opposingphases while the transistors M4A-M5B derive power from the input voltageat the low-voltage terminal VI. Powering the gate drivers from aparallel charge-transfer path, which is operating with opposing phase,eliminates one voltage follower in each case.

Yet another advantage of the dual-phase configuration of the secondcascade-multiplier 40 is that those voltage followers that do remain nolonger consume power. This is because those transistors that still usevoltage followers as part of their gate drives, namely the transistorsM0A, M2A, M5A, M0B, M2B, M5B, are no longer conducting at the time thatvoltage is being dropped across their corresponding voltage followers.With no current flowing, power loss becomes impossible. As a result,those voltage followers that remain operate far more efficiently thantheir counterparts in the first cascade-multiplier 30.

In comparing the first and second cascade-multipliers 30, 40, it shouldbe apparent that there is something else missing in the second cascademultiplier 40: namely, high-voltage gate-drivers 35. These high-voltagegate-drivers 35 are yet another casualty of having more than onecharge-transfer path.

Because of the more efficient voltage followers and the elimination ofhigh-voltage gate-drivers 35, the energy required to drive the gates ina dual-phase design is actually less than the energy required in asingle-phase design. This is true even though there are many moreindividual components in the dual-phase design.

As in the single-phase construction of FIG. 1 , it takes two fullclock-cycles for a charge to traverse the second cascade-multiplier 40and reach the load 18. However, in the dual-phase construction, thereare two charge-transfer paths between the source 16 and the load 18,instead of just one. Moreover, the two charge-transfer paths areoperated out-of-phase. This means that when one is idle, the other canbe busy.

For example, consider what happens to a charge after it enters a firstcharge-transfer path at the input of the second cascade-multiplier 40.

During each state transition, the charge hops from the anode of one pumpcapacitor to the anode of the next pump capacitor. Thus, by the end of afirst state transition, the charge is at the anode of a first pumpcapacitor C3B. By the end of a second state transition, the charge is atthe anode of a second pump capacitor C2B. By the end of a third statetransition, the charge is at the anode of a third pump capacitor C1B.Finally, at the end of a fourth state transition, the charge reaches theload 18.

Similarly, in a second charge-transfer path, the same procedure occurs.A charge hops from one anode to the next along first, second, and thirdpump capacitors C3B, C2B, C1B of the second charge-transfer path.However, the second charge-transfer path operates 180 degreesout-of-phase from the first charge-transfer path. As a result, a pathfor charge always exists between the source 16 and the load 18.

The above described dual-phase second cascade-multiplier 40 is one ofmany different implementations.

For example, FIG. 8 illustrates a third cascade-multiplier 50 that alsohas two charge-transfer paths. The third cascade-multiplier 50 featuresinner switches M1A, M3A, M1B, M3B that are able to support twice theoutput voltage as well as their corresponding gate drivers 35. As aresult, it is possible to omit the cascoded switches M2A, M4A, M2B, M4Bin the second cascade-multiplier 40. This reduces control complexity andperhaps improving robustness.

Additionally, the third cascade-multiplier 50 features pump capacitorsC3A, C3B that are pumped in series with their corresponding pumpcapacitors C1A, C1B instead of being pumped in parallel as in the secondcascade-multiplier 40. The series arrangement reduces the voltage acrossthe pump capacitors C3A, C3B.

For example, a five-volt output voltage at the high-voltage terminal VOresults in ten volts across the pump capacitors C3A, C3B in FIG. 8 .This is significantly lower than the fifteen volts across thecounterpart pump capacitors in FIG. 6 . Due to the similarity betweenthe second and third cascade multipliers 40, 50, the thirdcascade-multiplier 50 operates as described in connection with FIG. 7 .

A voltage follower 36A maintains the supply voltage for the driver 34that drives the transistor M0A. In the illustrated embodiment, thevoltage follower 36A is a transistor whose gate connects to a biasvoltage V1a.

A voltage difference between the voltage at the low-voltage terminal VIand the voltage at the high-voltage terminal VO is what ultimatelysupports the bias voltage V1a. However, this voltage difference is aptto fluctuate, much to the detriment of proper operation. Therefore, totame this fluctuating voltage difference, it is useful to connect theanode of a Zener diode 37A to the high-voltage terminal VO and toconnect the cathode of the Zener diode 37A to the low-voltage terminalVI through a voltage-absorbing resistor 39A. In this configuration, thecathode of the Zener diode 37A remains at a constant voltage V1a. Byalso connecting the gate of the voltage follower 36A to the cathode ofthe Zener diode 37A, it becomes possible to bias the voltage follower36A at this constant voltage.

A similar principle is used to maintain constant bias voltages V1b, V4a,V4b the remaining low-voltage drivers 34 in the cascade multiplier 50use a similar principle in which a resistor absorbs fluctuations so thatthe voltage across the Zener diode can be clamped to a constant valuethat can then be provided to the relevant voltage follower's gate.

The capacitor voltages have uses other than promoting efficientgeneration of gate-driving signals. For example, the capacitor voltagescan also be used to efficiently drive the phase signals that drive thecapacitors. Two examples of a phase generator 110 for carrying this outare shown in FIGS. 10-11 . These are suitable for use with thedual-phase third cascade-multiplier 50 shown in FIGS. 8 and 9 .

There are other ways to maintain a constant supply voltage that do notrequire the arrangement used for the low-voltage driver 34 that drivesthe transistor M0A. An example is that shown in FIG. 9 for maintaining aconstant supply voltage for the high-voltage driver 35 that drives thetransistors M1A, M1B.

In FIG. 9 , there exists a voltage difference between the anode of apump capacitor C3A and a voltage provided at a voltage-supply terminalVDR. This voltage difference is what ultimately supports the supplyvoltage that the high-voltage driver 35 uses in order to move charge tothe gate of the transistor M1A. However, this voltage differencetransitions between first and second anode voltages. For example, thevoltage Vca at the anode of the pump capacitor C3A changes by a factorof two during normal operation, between VO and 2VO.

To harness this voltage difference as a supply voltage, the high-voltagedriver 35 relies on a voltage-following capacitor Ca and a drive diodeDa that connect between the anode of the pump capacitor C3A and thevoltage-supply terminal VDR.

The voltage-following capacitor's cathode connects to that of the pumpcapacitor C3A. It therefore follows this voltage. Meanwhile, thevoltage-following capacitor's anode connects to the cathode of the drivediode Da, the anode of which connects to the voltage-supply terminalVDR.

The voltage at the voltage-supply terminal VDR is selected such thedrive diode Da transitions between being forward and reversed biased asthe cathode voltage Vca transitions between its two values. In addition,the voltage at the at the voltage-supply terminal VDR is selected suchthat an appropriate gate-drive voltage, for example five volts, isavailable to the high-voltage driver 35.

At the first cathode voltage, the drive diode Da becomes forward biased.As a result, charge from the voltage-supply terminal VDR charges thevoltage-following capacitor Ca. By connecting the high-voltage driver 35between the anode and cathode of the voltage-following capacitor Ca, itbecomes possible to provide a steady supply voltage for the high-voltagedriver 35.

The voltage-following capacitor Ca can be provided externally or it canbe integrated into a die.

The voltage-supply terminal VDR can be implemented by providing a linearregulator that regulates the voltage present at the high-voltageterminal VO. Alternatively, the voltage-supply terminal VDR can beimplemented by providing a connection to internal charge pump nodehaving a suitably high voltage (with an optional linear regulator).

It is apparent from inspection of the circuitry that thevoltage-following capacitor Ca acts effectively as a proxy for the pumpcapacitor C3A but with a voltage difference across it that is morereadily controllable to ensure an adequate supply voltage. Such controlis achievable by controlling the voltage at the voltage-supply terminalVDR.

An adequate supply voltage is particularly important for avoiding lossesin the transistor M1A. This is because even if a supply voltage is highenough to at least cause the transistor to conduct, such a voltage willnot result in a high enough electric field to create a broad channelthrough which current can flow with minimal resistance. This phenomenonis manifested by the inverse relationship between RDSON and gatevoltage.

Although the use of circuitry as shown in FIG. 9 provides a way toensure an adequate supply voltage, it is not without cost. First, thereis the need to supply additional capacitors. This consumes die area (oran external ceramic capacitor). Second, the voltage to charge thesecapacitors comes from regulating a high-voltage source down to a moreappropriate voltage, for example, using a linear regulator. This resultsin loss.

In FIG. 10 , the phase generator 110 receives an output voltage from thehigh-voltage terminal VO and produces first, second, third, and fourthphase voltages VP1-VP4. The first and second phase voltages VP1, VP2correspond to the first phase of the third cascade-multiplier 50 whilethe third and fourth phase voltages VP3, VP4 correspond to the secondphase of the third cascade-multiplier 50.

The phase generator 110 features four transistor pairs. Each transistorpair generates one of the phase voltages VP1-VP4. A firsttransistor-pair MH1, ML1 generates the first phase-voltage VP1; a secondtransistor-pair MH2, ML2 generates the second phase-voltage VP2; a thirdtransistor-pair MH3, ML3 generates the third phase-voltage VP3; and afourth transistor-pair MH4, ML4 generates the fourth phase-voltage VP4.In each transistor pair, the high-side transistor (e.g. MH1) is a PMOSdevice while the low-side transistor (e.g. ML1) is an NMOS device.

Separate gate drivers, each of which relies on the voltage at thehigh-voltage terminal VO to maintain a supply voltage, control eachtransistor MH1-MH4, ML1-ML4 in the phase generator 110, thereby allowingtri-state operation of each transistor pair. In a first state, a firsttransistor of the transistor-pair is conducting, and a second transistorof the pair is non-conducting. In a second state, the first transistorof the pair is non-conducting and the second transistor of the pair isconducting. In the third state, which occurs between the first andsecond states, both the first and second transistors of the pair arenon-conducting.

The gate drivers can be implemented using numerous circuit topologies,such as the tapered gate driver illustrated in FIG. 4 . Each gate driverreceives a driver signal with a label beginning with either an “A” or a“B.” A controller 112 generates driver signals AL1, BL1, AL2, BL2 tocontrol low-side transistors ML1, ML2, ML3, ML4 respectively and driversignals BH1, AH1, BH2, AH2 to control high-side transistors MH1, MH2,MH3, MH4 respectively at times dictated by a clock signal provided at aclock input CLK.

In normal operation, the phase generator 110 cycles between a firststate and a second state at a specific frequency. The third state occursbetween each transition between a first and second state.

Following commencement of the first state, the gate drivers that receivea “B” signal activate their corresponding transistors and the gatedrivers that receive an “A” signal de-activate their correspondingtransistors. Consequently, the first and third phase voltages VP1, VP3are equal to the output voltage at the high-voltage terminal VO whilethe second and fourth phase voltages VP2, VP4 are equal to zero volts.

In contrast, following commencement of the second state, the gatedrivers that receive a “B” signal de-activate their correspondingtransistors and the gate drivers that receive an “A” signal activatetheir corresponding transistors. Consequently, the first and third phasevoltages VP1, VP3 are equal to zero volts while the second and fourthphase voltages VP2, VP4 are equal to the output voltage at thehigh-voltage terminal VO.

FIG. 11 illustrates an alternative phase generator 110 that receives anoutput voltage from the high-voltage terminal VO and produces first,second, third, and fourth phase voltages VP1-VP4. In a dual-phasedesign, the first and third phase voltages VP1, VP3 are in phase and thesecond and fourth phase voltages VP2, VP2 are in phase. Consequently,the first and third phase voltages VP1, VP3 are shorted together and thesecond and fourth phase voltages VP2, VP4 are shorted together. Acontroller 112 generates driver signals A1, B2 to control low-sidetransistors ML1, ML2 respectively and driver signals B1, AH to controlhigh-side transistors MH1, MH2 respectively at times dictated by a clocksignal provided at a clock input CLK.

Additionally, the phase generator 110 shown in FIG. 11 implements thehigh-side transistors MH1, MH2 using NMOS transistors instead of usingPMOS transistors, as was the case in FIG. 10 . The higher mobility ofelectrons in NMOS transistors allows the high-side transistors MH1, MH2to be made smaller. This reduces the energy required to activate them.Because NMOS transistors require a gate voltage higher than their sourcevoltage to activate, the high-side transistors MH1, MH2 derive thisboost voltage from the pump capacitors within the cascade multiplierthat the phase generator 110 is driving. These pump capacitors connectto the power inputs NC1, NC2.

For example, if the phase generator 110 is coupled to the thirdcascade-multiplier 50, then the gate driver of the high-side transistorMH1 is coupled to the positive terminal of the pump capacitor C1A fromphase one. In contrast, the gate driver of the high-side transistor MH2is coupled to the positive terminal of the pump capacitor C1B from phasetwo. Therefore, each gate driver and its corresponding high-sidetransistor is powered by a pump capacitor from a distinct parallelcharge-transfer path. These pump capacitors connect to the power inputsNC1, NC2, as shown in FIGS. 8-9 .

The phase generator 110 shown in FIG. 11 operates in a manner similar tothat described in connection with FIG. 10 . The differences mainly arisefrom the shorted phase voltages and boosted high-side transistors MH1,MH2.

FIG. 12 shows yet another phase generator 110 that is similar to thatshown in FIG. 11 but with the voltage relied upon to provide the supplyvoltage for the high-side transistors MH1, MH2 no longer being suppliedfrom the pump capacitors. Instead, the supply voltage is provided usinga voltage-following capacitor and drive diode in a manner similar tothat described in connection with FIG. 9 .

A number of alternatives to the switched capacitor power converterdesigns discussed make use of the approaches embodied in those designs.For example, the converter illustrated in FIG. 13 is a dual-phaseseries-parallel switched capacitor circuit 60 that includes some gatedrivers that are powered by capacitors in either the samecharge-transfer path or a parallel charge-transfer path.

The switched capacitor circuit 60 includes a pair of phases. A firstphase includes capacitors C1C-C3C, odd transistors M1C-M7C, and eventransistors M2C-M12C. Similarly, a second phase includes capacitorsC1D-C3D, odd transistors M1D-M7D, and even transistors M2D-M12D. All ofthe transistors coupled with signals having an “A” prefix throughcorresponding gate drivers are activated and de-activated at the sametime; as is the case for all of the transistors coupled with signalshaving a “B” prefix through corresponding gate drivers.

The switched capacitor circuit 60 produces an output voltage at itshigh-voltage terminal VO that is four times lower than an input voltageat the low-voltage terminal VI by cycling between a first state and asecond state at a specific frequency. During the first state, the firstphase odd transistors M1C-M7C and the second phase even transistorsM2D-M12D are activated while the first phase even transistors M2C-M12Cand the second phase odd transistors M1D-M7D are de-activated. Thisswitch activation pattern places the second phase capacitors C1D-C3D inparallel with the load 18 and places a series arrangement of the firstphase capacitors C1C-C3C in between the source 16 and the load 18.

In contrast, during the second state, the first phase odd transistorsM1C-M7C and the second phase even transistors M2D-M12D are de-activatedwhile the first phase even transistors M2C-M12C and the second phase oddtransistors M1D-M7D are activated. This switch activation pattern placesthe first phase capacitors C1C-C3C in parallel with the load 18 andplaces a series arrangement of the second phase capacitors C1D-C3D inbetween the source 16 and the load 18.

Unlike either of the dual-phase cascade multipliers 40 or 50, within asingle phase of the switched capacitor circuit 60, the gate driversderive their power from capacitors in both phases. For example, the gatedrivers for the corresponding transistors M1C, M3C, M5C are powered fromthe capacitors C1C, C2C, C3C, respectively while the gate drivers forthe corresponding transistors M4C, M8C, M12C are powered from thecapacitor C1D.

Furthermore, the voltage stress across the transistors in aseries-parallel switched capacitor power converter can be quite high incomparison to cascade multipliers. Assuming twenty-volt input voltage atthe low-voltage terminal VI then the maximum voltage across thetransistors M12C, M12D is fifteen volts. In this embodiment, thegate-to-source voltage is always five volts and the gate drivers for thetop PMOS transistors require two series connected voltage followers thatare biased using voltages V1c-V2d.

Although described in the context of single-phase and dual-phaseconverters, it should be understood that other multi-phase converterconfigurations can be used. For example, a four-phase cascade multipliercan be constructed by placing two copies of the secondcascade-multiplier 40 in parallel and shifting their respective clocksby ninety degrees. Adding an even number of phases is straightforwardbecause every subsequent pair of phases can be run in isolation.

However, if the switched capacitor power converter includes an oddnumber of phases, it is a little more difficult to power gate driversfrom capacitors in different parallel charge-transfer paths. In thiscase, each gate driver draws power from capacitors in multiple parallelcharge-transfer paths, as compared to a single parallel charge-transferpath in the even-numbered phase case.

In general, switched-capacitor power-converters feature a large numberof switches and capacitors. By necessity, at least a few of the switchesare floating. This means that neither switch terminal is attached to aconstant electric potential. A switched-capacitor power-converter thathas at least one floating switch can benefit by deriving power from thesame charge-transfer path or a parallel charge-transfer path. Examplesof such switched-capacitor power-converters include the cascademultiplier, series-parallel, parallel-series, Fibonacci, andvoltage-doubler topologies.

The switched-capacitor power-converters and the associated gate driversillustrated herein can all be integrated on one or more semiconductorsubstrates.

If all of the transistors are integrated on a single substrate and anyof the transistors connect to a floating voltage, then the transistorsmust be isolated from the substrate. For example, in a CMOS process,NMOS transistors are typically formed in a p-type substrate. Thesedevices can only float if the bulk of the NMOS transistors is isolatedfrom the substrate. If this were not the case, then an alternativepossibility would be to use multiple semiconductor substrates.

The capacitors in a switched-capacitor power-converter can either beintegrated, discrete, or a combination thereof. The discrete capacitorsare typically multi-layer ceramic capacitors while the integratedcapacitors are typically planar or trench capacitors. Integratedcapacitors can be integrated on the same wafer with their switches, on awafer separate from their switches, or on a combination thereof. Forthose cases in which the capacitors and switches are on differentwafers, there exit various attachment methods, some of which remove thepin-count limitation of the overall converter.

The ability to re-purpose the pump capacitors is of benefit when theswitched-capacitor power-converter uses either integrated capacitors ordiscrete capacitors.

If discrete capacitors are used, then each capacitor uses at least onepin of an integrated circuit. Having to add extra pins for the gatedriver is disadvantageous because, for a given die area, only a limitednumber of pins is available.

An advantage of integrated capacitors is that they do not requireallocation of pins from a limited supply of pins. On the other hand,integrated capacitors consume considerable die area to achieve thenecessary levels of capacitance. They are therefore expensive tomanufacture.

Typically, a controller produces control signals for activating andde-activating the switches within a switched-capacitor power-converter.For example, in most of the embodiments described above, a controllercould have generated the drive signals that are labeled with an “A” or a“B” prefix.

By controlling the “on” and “off” times of the individual switches, acontroller can provide many functions. Among these functions are theability to regulate the output voltage, the ability to shut off thepower converter in the event of a fault condition, and the ability tochange the gain of the switched capacitor network.

The cascade multipliers 30, 40, 50, 60 described in connection withFIGS. 1-13 find use as a constituent element of a power converter 62 asshown in FIG. 14 .

The illustrated power converter 62 features a first element 64 and asecond element 66. First terminals 68 of the first element 64 connect toa voltage source 70. Second terminals 72 of the first element 64 connectto first terminals 74 of the second element 66. Second terminals 76 ofthe second element 66 connect to an output capacitor 78 that is inparallel with a load 80.

A controller 82 provides control signals to the first and secondelements 64, 66 and receives feedback signals from the first and secondelements 64, 66 through first and second communication links 84, 86. Thecontroller does so in response to a clock signal received through itsclock port CLK and to instructions received through its I/O port IO.

In operation, the voltage source 70 presents a first voltage to thefirst element's first terminals 68. The controller 82 causes the firstelement 64 to transform this first voltage into an intermediate voltage.The second element 66 receives this intermediate voltage at its firstterminals 74 and transforms it into a second voltage that it maintainsat its second terminals 76 and makes it available to the outputcapacitor 78 and the load 80.

In some embodiments, the first element 64 is a regulator and the secondelement 66 is the switched-capacitor circuit that comprises one of thecascade multipliers 30, 40, 50, 60 described herein. In otherembodiments, the first element is the switched-capacitor circuit thatcomprises one of the cascade multipliers 30, 40, 50, 60 described hereinand the second element is regulator.

In some embodiments, the regulator is one that has an inductive elementthat can be used in connection with controlling charge flow within thecapacitors of the switched-capacitor circuit. Examples of regulatorsthat can be used in the power converter 62 include buck converters,boost converters, and buck/boost converters.

Power converters of the type shown in FIG. 14 are described in detail inU.S. Pat. Nos. 8,860,396, 8,743,553, 8,723,491, 8,503,203, 8,693,224,8,724,353, 8,619,445, 9,203,299, 9,742,266, 9,041,459, Publication No.2017/0085172, U.S. Pat. No. 9,887,622, 9,882,471, PCT Publication No.WO2017161368, PCT Publication No. WO2017/091696, PCT Publication No.WO2017/143044, PCT Publication No. WO2017/160821, PCT Publication No.WO2017/156532, PCT Publication No. WO2017/196826, and U.S. PublicationNo. 2017/0244318, the contents of which are all incorporated herein byreference.

Generally speaking, a non-abstract computer accessible storage mediummay include any non-transitory storage media accessible by a computerduring use to provide instructions and/or data to the computer. Forexample, a computer accessible storage medium may include storage mediasuch as magnetic or optical disks and semiconductor memories. Such anon-abstract computer accessible storage medium can be used to storeinformation representative of the power converter or components thereoffor use, hereafter referred to as the “system,” in a manufacturingprocess.

Generally, a non-abstract database representative of the system may be adatabase or other data structure that can be read by a program and used,directly or indirectly, to fabricate the hardware comprising the system.For example, the database may be a behavioral-level description orregister-transfer level (RTL) description of the hardware functionalityin a high-level design language (HDL) such as Verilog or VHDL. Thedescription may be read by a synthesis tool that may synthesize thedescription to produce a netlist comprising a list of gates from asynthesis library. The netlist comprises a set of gates that alsorepresent the functionality of the hardware comprising the system. Thenetlist may then be placed and routed to produce a data set describinggeometric shapes to be applied to masks. The masks may then be used invarious semiconductor fabrication steps to produce a semiconductorcircuit or circuits corresponding to the system. In other examples,Alternatively, the database may itself be the netlist (with or withoutthe synthesis library) or the data set.

Various features, aspects, and embodiments of switched-capacitorpower-converters have been described herein. The features, aspects, andnumerous embodiments described are susceptible to combination with oneanother as well as to variation and modification, as will be understoodby those having ordinary skill in the art. The present disclosure shouldtherefore be considered to encompass such combinations, variations, andmodifications. Additionally, the terms and expressions that have beenemployed herein are used as terms of description and not of limitation.There is no intention, in the use of such terms and expressions, ofexcluding any equivalents of the features shown and described, orportions thereof. It is recognized that various modifications arepossible within the scope of the claims. Other modifications,variations, and alternatives are also possible. Accordingly, the claimsare intended to cover all such equivalents.

It is to be understood that the foregoing description is intended toillustrate and not to limit the scope of the invention, which is definedby the scope of the appended claims. Other embodiments are within thescope of the following claims.

The invention claimed is:
 1. An apparatus comprising aswitched-capacitor power-converter, wherein said switched-capacitorpower-converter comprises an input, an output, a first plurality ofswitches, a second plurality of switches, and gate-driving circuits,each of which corresponds to a switch from said first plurality ofswitches, wherein each gate-driving circuit uses charge from a selectedpump capacitor from a plurality of pump capacitors to operate acorresponding one of said switches from said first plurality ofswitches, wherein said first plurality of switches comprises a firstswitch, wherein said second plurality of switches comprises a secondswitch, wherein, during clocked operation of said switched-capacitorpower-converter, said first plurality of switches transitions betweendifferent states, each of which corresponds to a particularinterconnection of said pump capacitors, said pump capacitors includinga first pump capacitor, wherein, during clocked operations, said firstswitch closes, thereby establishing a connection with said first pumpcapacitor, wherein, prior to said first switch closing, said secondswitch closes, wherein as a result of closure of said second switch,said first pump capacitor is pre-charged by the time said first switchcloses.
 2. The apparatus of claim 1, wherein said second switch isconnected such that, when said second switch closes, a voltage arisesacross said first pump capacitor.
 3. The apparatus of claim 1, whereinsaid second switch connects to an anode of said first pump capacitor. 4.The apparatus of claim 1, wherein closing said second switch connectssaid first pump capacitor to a phase voltage.
 5. The apparatus of claim4, wherein said second switch and said first switch are synchronized inoperation.
 6. The apparatus of claim 5, wherein said first switch andsaid second switch close concurrently.
 7. The apparatus of claim 5,wherein said second switch closes before said first switch closes. 8.The apparatus of claim 7, wherein there exists a fixed time intervalbetween closing said second switch and closing said first switch.
 9. Theapparatus of claim 1, further comprising a pre-charging circuitconfigured to limit voltage across said switches from said firstplurality of switches during power-up of said switched-capacitorpower-converter.
 10. The apparatus of claim 1, further comprising aphase generator comprising phase switches, wherein said second switch isone of said phase switches.
 11. The apparatus of claim 10, wherein saidphase generator is configured to provide first and second phasevoltages, wherein said second switch provides said first phase voltageupon closure thereof, and wherein said phase generator further comprisesa third switch that, when closed provides said second phase voltage,wherein said first plurality of switches comprises a first subset ofswitches and a second subset of switches, wherein switches in said firstsubset open and close together, wherein switches in said second subsetopen and close together at times that differ from times at which saidswitches in said first subset open and close together, wherein, saidfirst switch is in said first subset, wherein said second switch issynchronized with switches in said first subset, and wherein said thirdswitch is synchronized with switches in said third subset.
 12. Theapparatus of claim 11, wherein, as a result of being synchronized withswitches in said first subset, said second switch closes prior toclosure of all switches in said first subset, and wherein, as a resultof being synchronized with switches in said second subset, said thirdswitch closes prior to closure of all switches ins said first subset.13. The apparatus of claim 1, further comprising a control block thatcomprises circuitry that is configured to provide a first plurality ofdrive signals and to provide a second plurality of drive signals,wherein each drive signal from said first plurality of drive signals isconnected to a one of the gate-driving circuit circuits that drives agate of a transistor from a first plurality of transistors, wherein eachdrive signal from said second plurality of drive signals is connected toa one of the gate-driving circuit circuits that drives a gate of atransistor from a second plurality of transistors, wherein said drivesignals from said first plurality of drive signals cooperate to causeall transistors that are in said first plurality of transistors to closetogether following closure of said second switch, and wherein said drivesignals from said second plurality of drive signals is configured tocause all transistors in said second plurality of transistors to closetogether following closure of a third switch from said second pluralityof switches.
 14. The apparatus of claim 13, wherein said circuitrycomprises a level shifter that is configured to receive first and secondvoltages and to transform said first and second voltages into third andfourth voltages, wherein said level shifter is configured to present avoltage difference that is equal to a difference between said third andfourth voltage to a the gate terminal of a the transistor that is fromsaid first plurality of transistors.
 15. The apparatus of claim 1,further comprising a phase generator comprising said second plurality ofswitches, said phase generator being configured to provide a timevarying voltage level to one terminal of each of said pump capacitors,wherein said phase generator is configured to generate a voltage levelfor at least one pump capacitor in a first charge-transfer path using avoltage from a pump capacitor in a second charge-transfer path.
 16. Anapparatus comprising a switched-capacitor power-converter that comprisesfirst and second pluralities of switches and gate-driving circuitscorresponding to said switches in said first plurality of switches, saidgate-driving circuits being configured to rely on charge on pumpcapacitors to cause said switches from said first plurality of switchesto transition between states, wherein, said switched-capacitorpower-converter undergoes clocked operation that consists of consecutiveclock cycles during each of which a switch from said second plurality ofswitches connects to a first pump capacitor from the pump capacitors andthen a first switch from said first plurality of switches connects tosaid first pump capacitor.
 17. The apparatus of claim 16, wherein, whensaid switch from said second plurality of switches connects to saidfirst pump capacitor, said first pump capacitor begins to charge. 18.The apparatus of claim 16, wherein said switch from said secondplurality of switches connects to both said first pump capacitor and asecond pump capacitor, and wherein, after said switch from said secondplurality of switches has closed, a second switch from said firstplurality of switches connects to a second pump capacitor.
 19. Theapparatus of claim 16, wherein while said switch from said secondplurality of switches is connected to said first pump capacitor, asecond pump capacitor is being discharged.
 20. An apparatus comprising aswitched-capacitor power-converter that comprises first and secondpluralities of switches and gate-driving circuits corresponding to saidswitches in said first plurality of switches, said gate-driving circuitsbeing configured to rely on charge stored on pump capacitors to causesaid switches from said first plurality of switches to transitionbetween states, wherein, said switched-capacitor power-converterundergoes clocked operation that consists of consecutive clock cycles,each of which includes a portion during which at most a second switchfrom said second plurality of switches is connected to said pumpcapacitors.
 21. An apparatus comprising: a switched-capacitorpower-converter comprising an input port and an output port, a first anda second plurality of switches to be interconnected with a plurality ofcapacitors, and gate-driving circuits, a particular gate-driving circuitof the gate-driving circuits to correspond to a switch from the firstplurality of switches, wherein the particular gate-driving circuit usescharge from a selected donor capacitor of the plurality of capacitors tooperate a corresponding one of the switches from the first plurality ofswitches, wherein the first plurality of switches comprises a firstswitch and the second plurality of switches comprises a second switch,wherein, during clocked operation of the switched-capacitorpower-converter, the first plurality of switches transitions betweendifferent states, a particular state of the different states tocorrespond to a particular interconnection of the plurality ofcapacitors, wherein, during the clocked operation of theswitched-capacitor power-converter, the first switch closes to establisha connection with a first donor capacitor of the plurality ofcapacitors, wherein, prior to the first switch closing, the secondswitch closes, and wherein the first donor capacitor is to be at leastpartially charged by the time the first switch closes.
 22. The apparatusof claim 21, wherein the first donor capacitor is to be charged uponclosure of the second switch.
 23. The apparatus of claim 21, wherein thefirst donor capacitor is to be pre-charged by the time the first switchcloses.
 24. The apparatus of claim 21, wherein the donor capacitorcomprises a pump capacitor.
 25. The apparatus of claim 21, wherein thedonor capacitor comprises a voltage-following capacitor.
 26. Theapparatus of claim 21, wherein the selected donor capacitor comprisesthe first donor capacitor.
 27. The apparatus of claim 21, and furthercomprising a controller to generate control signals, the control signalsto include at least a first plurality of drive signals and a secondplurality of drive signals, wherein the first plurality of drive signalsto facilitate contemporaneous closure of the first plurality of switchesupon closure of the second switch, and wherein the second plurality ofdrive signals to facilitate contemporaneous closure of the secondplurality of switches upon closure of an additional switch of the secondplurality of switches.
 28. The apparatus of claim 27, wherein the firstplurality of drive signals and the second plurality of drive signals arenon-overlapping.
 29. The apparatus of claim 21, wherein the firstplurality of switches comprises at least a first subset of switches anda second subset of switches, wherein switches in the first subset ofswitches to open and close together at times that differ from times atwhich switches in the second subset to open and close together.
 30. Theapparatus of claim 29, wherein the second switch is to be synchronizedwith the switches in the first subset of switches.
 31. The apparatus ofclaim 21, wherein the first switch and the second switch to closeconcurrently.
 32. The apparatus of claim 21, wherein the first switch toclose after or prior to closure of the second switch.
 33. The apparatusof claim 21, wherein the clocked operation to include a fixed timeinterval between closure of the second switch and closure of the firstswitch.
 34. An apparatus comprising: a switched-capacitorpower-converter having a first plurality of switches and a secondplurality of switches, the first plurality of switches to comprise afirst subset of switches and a second subset of switches; and aplurality of gate drivers coupled to corresponding switches of the firstor the second plurality of switches to facilitate one or more statetransitions of the corresponding switches based, at least in part, oncharge stored on respective capacitors, a particular capacitor of therespective capacitors to be coupled to a negative node of acorresponding gate driver of the plurality of gate drivers, wherein theswitched-capacitor power-converter to carry out a clocked operation viaconsecutive clock cycles, wherein, during the clocked operation, thefirst and the second subsets of switches to close concurrently and thesecond subset of switches to open prior to opening of all switches inthe first plurality of switches, and wherein the clocked operation toimplement a time interval during which signals with respect to the firstand the second plurality of switches are non-overlapping.
 35. Theapparatus of claim 34, wherein the time interval to occur between theone or more state transitions.
 36. The apparatus of claim 34, whereinthe respective capacitors comprise one or more donor capacitors.
 37. Theapparatus of claim 34, wherein the respective capacitors comprise one ormore voltage-following capacitors.
 38. The apparatus of claim 34,wherein the respective capacitors comprise one or more pump capacitors.39. The apparatus of claim 34, wherein the first or the second pluralityof switches to include one or more Zener-type diodes.
 40. The apparatusof claim 34, wherein, during the clocked operation, a voltage across theone or more Zener-type diodes to be respectively clamped to asubstantially constant voltage.
 41. The apparatus of claim 34, andfurther comprising an inductive element to facilitate at least partialcontrol of a charge flow within the switched-capacitor power-converter.